SDMA Channels

SDMA Channels

The CP implements two dedicated virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI, and I2C—one for each transmitter and receiver. An additional four virtual SDMA channels are assigned to the programmable independent DMA (IDMA) channels.
Figure data flow paths. Data from the peripheral controllers can be routed to external RAM
using the 60x bus (path 1) or the local bus (path 2).



On a path 1 access, the SDMA channel must acquire the external system bus. On a path 2 access, the local bus is acquired and the access is not seen on the external system bus. Thus, the local bus transfer occurs at the same time as other operations on the external 60x system bus.

The SDMA channel can be assigned big-endian (Freescale) or little-endian format for accessing buffer data. These features are programmed in the receive and transmit registers associated with the FCCs, MCCs, SCCs, SMCs, SPI, and I2C.
If a 60x or local bus error occurs on a CP-related access by the SDMA, the CP generates a unique interrupt in the SDMA status register (SDSR). The interrupt service routine then reads the appropriate DMA transfer error address register (PDTEA for the 60x bus or LDTEA for the local bus) to determine the address the bus error occurred on. The channel that caused the bus error is determined by reading the channel number from PDTEM or LDTEM. If an SDMA bus error occurs on a CP-related transaction, all CPM activity stops and the entire CPM must be reset in the CP command register (CPCR)

**The only user-accessible registers associated with the SDMA are the SDMA address registers, read-only register used for diagnostics in case of an SDMA bus error, the SDMA status register and the SDMA mask register.

for more details check the link below:
http://rapidshare.com/files/122891977/SDMA.pdf.html