Lattice CPLDs

Lattice CPLDs

Lattice offers a complete range of CPLDs, with two main product lines:
1.pLSI
2.isPLSI

pLSI is not in-system programmable.
ispLSI is in-system programmable.

The Lattice pLSI & ispLSI consist of three families of EEPROM CPLDs
(i)1000 series
(ii)2000 series
(iii)3000 series

These three families have different logic capacities and speed-performance.

Each chip consists of a collection of SPLD-like blocks, described in more detail later, and a global routing pool to connect blocks together.

pLSI & ispLSI 1000 series:

Lattice’s earliest generation of CPLDs is the pLSI 1000 series.

***Logic capacity ranges from about 1200 to 4000 gates.
***Pin-to-pin delays are 10 nsec.

pLSI & ispLSI 2000 series:

***Logic capacity ranges from about 600 to 2000 gates.
***These gates offer a higher ratio of macrocells to I/O pins and higher
speed-performance than the 1000 series.
***Pin-to-pin delays are 5.5 nsec.

pLSI & ispLSI 3000 series:


***Logic capacity ranges from up to 5000 gates.
***Pin-to-pin delays are about 10 - 15 nsec
***the 3000 series functionality is most similar to AMD’s Mach 4
***The 3000 series offers some enhancements over the other Lattice parts to support more recent design styles, such as JTAG boundary scan.

The general structure of a Lattice pLSI or ispLSI device is indicated in Figure 1



Figure1: Lattice pLSI & ispLSI Architecture

Around the outside edges of the chip are the bi-directional I/Os, which are connected both to the Generic Logic Blocks (GLBs) and the Global Routing Pool (GRP). As the fly-out on the right side of the figure shows, the GLBs are small PAL-like blocks that consist of an AND-plane, product term allocator, and macrocells. The GRP is a set of wires that span the entire chip and are available to connect the GLB inputs and outputs together. All interconnections pass through the GRP, so timing between levels of logic in the Lattice chips is fully predictable, much as it is for the AMD Mach devices.