Cypress FLASH370 CPLDs

Cypress FLASH370 CPLDs

Cypress has recently developed a family of CPLD products that are similar to both the AMD
and Lattice devices in several ways.

The Cypress CPLDs, called FLASH370 are based on FLASH EEPROM technology

It offer speed-performance of 8.5 to 15 nsec pin-to-pin delays.

The FLASH370 parts are not in-system programmable.

FLASH370 provides more I/Os than competing products, featuring a linear relationship between
the number of macrocells and number of bi-directional I/O pins.

The smallest parts have 32 macrocells and 32 I/Os.
The largest parts have 256 macrocells and 256 I/Os.



Figure1 : Architecture of Cypress FLASH370 CPLDs


Figure1 shows that FLASH370 has a typical CPLD architecture with multiple PAL-like
blocks and a programmable interconnect matrix (PIM) to connect them. Within each PAL-like
block, there is an AND-plane that feeds a product term allocator that directs from 0 to 16 product terms to each of 32 OR-gates. Note that in the feed-back path from the macrocell outputs to thePIM, there are 32 wires; this means that a macrocell can be buried (not drive an I/O pin) and yet the I/O pin that could be driven by the macrocell can still be used as an input. This illustrates another type of flexibility available in PAL-like blocks in CPLDs, but not present in normal PALs.